HBM Memory, Advanced Packaging and the Real Limits on AI Chips
SRF Capital Studio Research DeskFunding Intelligence, SRF Capital StudioThe binding limits on AI hardware sit in memory stacks, packaging lines and one Dutch toolmaker. How each chokepoint works, how fast it is easing, and who gets paid while it lasts.
Summary
- High bandwidth memory is the tightest input in AI hardware: three companies make it, all three pre-sold their 2026 output, and the market is estimated to rise from about $35 billion in 2025 to about $60 billion in 2026.
- Advanced packaging and EUV lithography are the other two chokepoints, each dominated by one company, and both take years rather than quarters to expand.
- For investors, the lesson is to value these positions by how long the shortage lasts, since capacity is now being added quickly at every one of them.
Most discussion of AI hardware starts and ends with the accelerator: which company designs the fastest one and how many it can ship. That misses where the physical limits actually are. A modern AI chip is a small system of parts, and the scarce parts are not the ones that make headlines.
Three constraints matter most. The memory stacked next to the processor, the packaging that joins them, and the lithography tools that print the circuits in the first place. Behind all three sits the geographic concentration of Taiwan.
What HBM memory is, and why AI needs it
A processor that does trillions of calculations a second is useless if data cannot reach it fast enough. Ordinary DRAM sits on a separate board and talks to the processor over a relatively narrow connection. High bandwidth memory, or HBM, solves that by stacking DRAM dies vertically, linking them with thousands of vertical connections called through-silicon vias, and placing the stack right beside the processor.
The numbers show how central it has become. Nvidia's B200 carries 192GB of HBM3E spread across eight stacks. Its successor platform, Rubin, is specified with up to 288GB of the newer HBM4. Each generation needs more stacks, taller stacks, or both.
In AI hardware, memory is no longer a component; it is the part that decides how many accelerators get built.
Why HBM supply cannot keep up
Only SK hynix, Samsung and Micron make HBM at volume. SK hynix has led, with Samsung and Micron gaining ground through 2026. In January 2026 all three said their HBM output for the year was already sold, largely under long-term agreements with accelerator makers and cloud companies.
Three things keep supply tight. First, yield: a stack is only as good as its weakest layer, so one bad die can scrap the whole stack, and yields trail ordinary DRAM. Second, wafer intensity: an HBM stack uses far more silicon per bit than standard memory, so shifting capacity to HBM shrinks total bit output. Third, lead time: new memory fabs and stacking lines take years to build and qualify.
Yole Group estimates HBM revenue at about $35 billion in 2025 and about $60 billion in 2026. TrendForce estimates demand grew about 130% in 2025 and will grow about 70% in 2026. The side effect is felt well outside data centres, because every wafer moved to HBM is a wafer not making memory for phones and laptops. We look at that price effect in our piece on the AI chip boom.
Custom chips do not escape the queue
The largest cloud companies now design their own AI chips, partly to cut dependence on a single accelerator vendor. That changes who designs the processor, but it does nothing for the memory problem. A Google or Amazon accelerator still needs HBM stacks from the same three suppliers, still goes through the same leading-edge foundry, and still waits for the same packaging lines.
So every new custom chip programme adds demand to the chokepoints rather than relieving them. For a memory maker, a more fragmented accelerator market is good news: more buyers competing for the same allocation strengthens its hand in price negotiations.
Advanced packaging: the step people forget
A finished AI accelerator is not one chip. It is a processor die and several HBM stacks mounted on a silicon interposer, which is then fixed to a substrate. TSMC's version of this process is called CoWoS, short for chip on wafer on substrate, and it has been the single most constrained step in the AI supply chain since 2023.
Industry estimates put CoWoS capacity at roughly 13,000 wafers a month at the end of 2023 and about 130,000 by the end of 2026, close to a tenfold rise. In September 2026 TrendForce reported that TSMC aims to double it again by 2028, mainly in Arizona and at a new site in Taiwan. Growth on that scale shows how acute the shortage was, and also that it is being attacked hard.
This is the stage where India has a foothold, though not yet at the leading edge. The assembly and test plants now running in Gujarat do conventional packaging, which is a different and far simpler business than CoWoS. Micron's Sanand plant, for example, assembles DRAM and NAND products, not HBM. The detail is in our Micron Sanand piece.
EUV lithography: one supplier
Every leading-edge chip, including every current AI accelerator, is patterned with extreme ultraviolet lithography, and ASML of the Netherlands is the only company that makes the machines. Its optics come from a single partner, Zeiss in Germany. ASML's newest High-NA systems are reported to cost around $380 million each.
This chokepoint behaves differently from the other two. HBM and packaging shortages are about volume and can be eased with capital. The ASML position is about capability, and no competitor is close. That is why export restrictions on ASML tools have become a central instrument of US and Dutch policy toward China.
Taiwan: the concentration beneath everything
Industry estimates put Taiwan's share of the most advanced logic chips at around 90%, and most of the world's CoWoS capacity is there too. The risk is not only military. In April 2024 a magnitude 7.4 earthquake struck eastern Taiwan and TSMC briefly evacuated fabs. Water shortages and grid stability are recurring concerns for plants that use enormous amounts of both.
New fabs in Arizona, Japan and Germany are real but will carry a minority of leading-edge output this decade. Diversification is happening at the margin, not at the core.
How we rate the chokepoints
The four supply chokepoints behind AI accelerators
| Chokepoint | Controlled by | Our risk rating | Is it easing? |
|---|---|---|---|
| HBM memory | SK hynix, Samsung, Micron | High | Slowly; 2026 output pre-sold, new capacity mostly from 2027 |
| CoWoS packaging | TSMC, primarily | High | Yes; capacity near 130,000 wafers a month by end-2026 |
| EUV lithography | ASML, with Zeiss optics | Critical | No; single supplier by design |
| Leading-edge logic fabs | TSMC, mostly in Taiwan | Critical | Slowly; overseas fabs add a minority share |
Scarcity earns high margins, but only for as long as the scarcity lasts.
What investors and founders should take from this
- Value chokepoints by duration. HBM and packaging are volume shortages that capital will ease; EUV is a capability monopoly that capital cannot easily replicate. Price them differently.
- Watch memory pricing for the turn. When HBM capacity catches up, memory margins will compress first. Track contract prices and supplier capacity plans, not just demand forecasts.
- Look for the suppliers to the suppliers. Substrates, bonding equipment, test sockets, specialty chemicals and clean-room services grow with every expansion, whoever wins the design race.
- Be realistic about India's role. Indian packaging plants can grow into more advanced work over time, but a founder pitching Indian HBM or CoWoS capacity this decade needs an unusually strong answer on technology and customers.
If you are assessing a hardware company whose plan depends on any of these inputs, a supply-side review belongs in due diligence alongside the financials. Our deep-tech practice works with founders on exactly that question.
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About the author
SRF Capital Studio Research Desk
Funding Intelligence, SRF Capital Studio
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